The present invention relates, generally, to EEPROM devices and methods for their fabrication and, more particularly, to single-poly EEPROM devices and to methods for their fabrication
Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the (electrically-erasable-programmable-read-only-memory) EEPROM device. In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode that may be formed in a region of the substrate referred to in the art as a control-gate region. The control-gate region is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode.
EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two transistor design or a three transistor design. A three transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a sense transistor. In a two transistor device, the functions of read and sense transistors are combined into a single transistor. To program PLD EEPROMs, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively low voltage Vpp is applied to the drain (bitline contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bitline to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the 5 floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bitline and a high voltage Vpp+ is applied to the control-gate. Under this bias condition, the high voltage applied to control-gate is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode.
As PLD EEPROM devices are scaled to smaller dimensions, the junction depth of the program junction region must be reduced. As used herein, the term xe2x80x9cprogram junction regionxe2x80x9d refers to a highly doped junction region in the substrate underlying the tunnel region and the control gate region. The program junction region is also known by various terms, such as the tunneling implant region. The most straightforward way to do reduce the depth of the program junction region is to simply reduce the doping concentration in the program junction region. Reducing the doping concentration in the program junction region, however, increases the depletion level during operation of the device. Large depletion levels, in turn, reduce the capacitive coupling to the floating gate electrode.
The reduction in capacitive coupling can be compensated for by increasing the capacitor area, but this can result in a larger EEPROM memory cell. Thus, maintaining a controlled amount of depletion in the program junction region, while avoiding increasing the capacitor area, requires that the doping concentration in the program junction region be kept at a high level. A high doping concentration, however, functions to undesirably increase the thickness of the capacitor dielectric layer during thermal oxidation processes used for device fabrication. A high surface doping concentration in the program junction region also causes low Fowler-Nordheim tunneling efficiency, which results in low programming current.
Accordingly, a need exists for an EEPROM device fabrication process that enables the fabrication of shallow junction devices, while maintaining uniform dielectric layer thickness and low surface doping concentration levels.
The present invention provides a process for fabricating an EEPROM device having a highly-doped shallow-junction program junction region with a retrograde doping concentration profile. The formation of a retrograde doping profile in the program junction region moves the peak doping concentration away from the substrate surface resulting in a relatively low surface doping concentration, while maintaining an overall high doping concentration in the program junction region. The relatively low surface doping concentration enables high programming efficiency by producing a large programming current. Additionally, the retrograde doping profile reduces the program junction threshold voltage and improves the capacitive coupling of the program junction region with an overlying floating-gate layer.
In accordance with the invention there is provided a process for fabricating an EEPROM device that includes providing a semiconductor substrate having a principal surface. A program junction region is formed in the semiconductor substrate that is characterized by doping concentration profile in which a maximum doping concentration is displaced away from the principal surface.
In another aspect of the invention, a process for fabricating a program junction region in an EEPROM device includes providing a semiconductor substrate having a principal surface and forming a first portion of a tunnel dielectric layer overlying the principal surface. Doping atoms are introduced into a tunnel region of the substrate and a second portion of the dielectric layer is formed to overlie the first portion of the dielectric layer. The maximum doping concentration of the doping atoms introduced into the tunnel region is displaced away from the principal surface.
In yet another aspect of the invention, a process for fabricating an EEPROM device includes providing a semiconductor substrate having a principal surface and forming a first doping concentration of a conductivity-determining doping in a tunnel region of the substrate. Then, a second doping concentration distribution of the conductivity-determining doping is formed in the tunnel region. The process is carried out in such a way that the maximum doping concentration of the second doping concentration distribution is displayed away from the principal surface.
In a still further aspect of the invention, an EEPROM device includes a semiconductor substrate having a principal surface and a dielectric layer on the principal surface. A program junction region resides in the semiconductor substrate adjacent to the dielectric layer. The program junction region is characterized by a doping concentration profile in which the maximum doping concentration is displaced away from the principal surface.